(VRV32I Register-Immediate Instructions
p0
ccopy_reg
_reconstructor
p1
(cvp_pack
Ip
p2
c__builtin__
object
p3
Ntp4
Rp5
(dp6
Vprop_count
p7
I11
sVname
p8
g0
sVprop_list
p9
(dp10
sVip_num
p11
I0
sVwid_order
p12
I0
sVrfu_dict
p13
(dp14
sVrfu_list
p15
(lp16
(V000_ADDI
p17
g1
(cvp_pack
Prop
p18
g3
Ntp19
Rp20
(dp21
Vitem_count
p22
I3
sg8
g17
sVtag
p23
VVP_IP011_P000
p24
sVitem_list
p25
(dp26
sg12
I0
sg15
(lp27
(V000
p28
g1
(cvp_pack
Item
p29
g3
Ntp30
Rp31
(dp32
g8
V000
p33
sg23
VVP_ISA_F011_S000_I000
p34
sVdescription
p35
Vaddi rd, rs1, imm[11:0]\u000ard = rs1 + Sext(imm[11:0])\u000aArithmetic overflow is lost and ignored
p36
sVpurpose
p37
VISA\u000aChapter 2.4
p38
sVverif_goals
p39
VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used
p40
sVcoverage_loc
p41
Visacov.rv32i_addi_cg.cp_rs1\u000aisacov.rv32i_addi_cg.cp_rd\u000aisacov.rv32i_addi_cg.cp_rd_rs1_hazard
p42
sVpfc
p43
I3
sVtest_type
p44
I3
sVcov_method
p45
I1
sVcores
p46
I56
sVcomments
p47
V
p48
sVstatus
p49
g48
sVsimu_target_list
p50
(lp51
sg15
(lp52
sVrfu_list_2
p53
(lp54
sg13
(dp55
Vlock_status
p56
I0
ssbtp57
a(V001
p58
g1
(g29
g3
Ntp59
Rp60
(dp61
g8
V001
p62
sg23
VVP_ISA_F011_S000_I001
p63
sg35
Vaddi rd, rs1, imm[11:0]\u000ard = rs1 + Sext(imm[11:0])\u000aArithmetic overflow is lost and ignored
p64
sg37
VISA\u000aChapter 2.4
p65
sg39
VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000aimmi value is +ve, -ve and zero\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of immi are toggled
p66
sg41
Visacov.rv32i_addi_cg.cp_rs1_value\u000aisacov.rv32i_addi_cg.cp_immi_value\u000aisacov.rv32i_addi_cg.cross_rs1_immi_value\u000aisacov.rv32i_addi_cg.cp_rs1_toggle\u000aisacov.rv32i_addi_cg.cp_immi_toggle
p67
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp68
sg15
(lp69
sg53
(lp70
sg13
(dp71
g56
I0
ssbtp72
a(V002
p73
g1
(g29
g3
Ntp74
Rp75
(dp76
g8
V002
p77
sg23
VVP_ISA_F011_S000_I002
p78
sg35
Vaddi rd, rs1, imm[11:0]\u000ard = rs1 + Sext(imm[11:0])\u000aArithmetic overflow is lost and ignored
p79
sg37
VISA\u000aChapter 2.4
p80
sg39
VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled
p81
sg41
Visacov.rv32i_addi_cg.cp_rd_value\u000aisacov.rv32i_addi_cg.cp_rd_toggle
p82
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp83
sg15
(lp84
sg53
(lp85
sg13
(dp86
g56
I0
ssbtp87
asVrfu_list_1
p88
(lp89
sg53
(lp90
sg13
(dp91
sbtp92
a(V001_XORI
p93
g1
(g18
g3
Ntp94
Rp95
(dp96
g22
I5
sg8
g93
sg23
VVP_IP011_P001
p97
sg25
(dp98
sg12
I1
sg15
(lp99
(V000
p100
g1
(g29
g3
Ntp101
Rp102
(dp103
g8
V000
p104
sg23
VVP_ISA_F011_S001_I000
p105
sg35
Vxori rd, rs1, imm[11:0]\u000ard = rs1 ^ Sext(imm[11:0])\u000aNote: this is a bitwise, not logical operation
p106
sg37
VISA\u000aChapter 2.4
p107
sg39
VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used
p108
sg41
Visacov.rv32i_xori_cg.cp_rs1\u000aisacov.rv32i_xori_cg.cp_rd\u000aisacov.rv32i_xori_cg.cp_rd_rs1_hazard
p109
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp110
sg15
(lp111
sg53
(lp112
sg13
(dp113
g56
I0
ssbtp114
a(V001
p115
g1
(g29
g3
Ntp116
Rp117
(dp118
g8
g115
sg23
VVP_ISA_F011_S001_I001
p119
sg35
Vxori rd, rs1, imm[11:0]\u000ard = rs1 ^ Sext(imm[11:0])\u000aNote: this is a bitwise, not logical operation
p120
sg37
VISA\u000aChapter 2.4
p121
sg39
VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000aimmi value is +ve, -ve and zero\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of immi are toggled
p122
sg41
Visacov.rv32i_xori_cg.cp_rs1_value\u000aisacov.rv32i_xori_cg.cp_immi_value\u000aisacov.rv32i_xori_cg.cross_rs1_immi_value\u000aisacov.rv32i_xori_cg.cp_rs1_toggle\u000aisacov.rv32i_xori_cg.cp_immi_toggle
p123
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp124
sg15
(lp125
sg53
(lp126
sg13
(dp127
g56
I0
ssbtp128
a(V002
p129
g1
(g29
g3
Ntp130
Rp131
(dp132
g8
g129
sg23
VVP_ISA_F011_S001_I002
p133
sg35
Vxori rd, rs1, imm[11:0]\u000ard = rs1 ^ Sext(imm[11:0])\u000aNote: this is a bitwise, not logical operation
p134
sg37
VISA\u000aChapter 2.4
p135
sg39
VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled
p136
sg41
Visacov.rv32i_xori_cg.cp_rd_value\u000aisacov.rv32i_xori_cg.cp_rd_toggle
p137
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp138
sg15
(lp139
sg53
(lp140
sg13
(dp141
g56
I0
ssbtp142
asg88
(lp143
sg53
(lp144
sg13
(dp145
sbtp146
a(V002_ORI
p147
g1
(g18
g3
Ntp148
Rp149
(dp150
g22
I4
sg8
g147
sg23
VVP_IP011_P002
p151
sg25
(dp152
sg12
I2
sg15
(lp153
(V000
p154
g1
(g29
g3
Ntp155
Rp156
(dp157
g8
V000
p158
sg23
VVP_ISA_F011_S002_I000
p159
sg35
Vori rd, rs1, imm[11:0]\u000ard = rs1 | Sext(imm[11:0])\u000aNote: this is a bitwise, not logical operation
p160
sg37
VISA\u000aChapter 2.4
p161
sg39
VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used
p162
sg41
Visacov.rv32i_ori_cg.cp_rs1\u000aisacov.rv32i_ori_cg.cp_rd\u000aisacov.rv32i_ori_cg.cp_rd_rs1_hazard
p163
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp164
sg15
(lp165
sg53
(lp166
sg13
(dp167
g56
I0
ssbtp168
a(V001
p169
g1
(g29
g3
Ntp170
Rp171
(dp172
g8
g169
sg23
VVP_ISA_F011_S002_I001
p173
sg35
Vori rd, rs1, imm[11:0]\u000ard = rs1 | Sext(imm[11:0])\u000aNote: this is a bitwise, not logical operation
p174
sg37
VISA\u000aChapter 2.4
p175
sg39
VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000aimmi value is +ve, -ve and zero\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of immi are toggled
p176
sg41
Visacov.rv32i_ori_cg.cp_rs1_value\u000aisacov.rv32i_ori_cg.cp_immi_value\u000aisacov.rv32i_ori_cg.cross_rs1_immi_value\u000aisacov.rv32i_ori_cg.cp_rs1_toggle\u000aisacov.rv32i_ori_cg.cp_immi_toggle
p177
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp178
sg15
(lp179
sg53
(lp180
sg13
(dp181
g56
I0
ssbtp182
a(V002
p183
g1
(g29
g3
Ntp184
Rp185
(dp186
g8
g183
sg23
VVP_ISA_F011_S002_I002
p187
sg35
Vori rd, rs1, imm[11:0]\u000ard = rs1 | Sext(imm[11:0])\u000aNote: this is a bitwise, not logical operation
p188
sg37
VISA\u000aChapter 2.4
p189
sg39
VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled
p190
sg41
Visacov.rv32i_ori_cg.cp_rd_value\u000aisacov.rv32i_ori_cg.cp_rd_toggle
p191
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp192
sg15
(lp193
sg53
(lp194
sg13
(dp195
g56
I0
ssbtp196
asg88
(lp197
sg53
(lp198
sg13
(dp199
sbtp200
a(V003_ANDI
p201
g1
(g18
g3
Ntp202
Rp203
(dp204
g22
I3
sg8
g201
sg23
VVP_IP011_P003
p205
sg25
(dp206
sg12
I3
sg15
(lp207
(V000
p208
g1
(g29
g3
Ntp209
Rp210
(dp211
g8
V000
p212
sg23
VVP_ISA_F011_S003_I000
p213
sg35
Vandi rd, rs1, imm[11:0]\u000ard = rs1 &  Sext(imm[11:0])\u000aNote: this is a bitwise, not logical operation
p214
sg37
VISA\u000aChapter 2.4
p215
sg39
VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used
p216
sg41
Visacov.rv32i_andi_cg.cp_rs1\u000aisacov.rv32i_andi_cg.cp_rd\u000aisacov.rv32i_andi_cg.cp_rd_rs1_hazard
p217
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp218
sg15
(lp219
sg53
(lp220
sg13
(dp221
g56
I0
ssbtp222
a(V001
p223
g1
(g29
g3
Ntp224
Rp225
(dp226
g8
V001
p227
sg23
VVP_ISA_F011_S003_I001
p228
sg35
Vandi rd, rs1, imm[11:0]\u000ard = rs1 &  Sext(imm[11:0])\u000aNote: this is a bitwise, not logical operation
p229
sg37
VISA\u000aChapter 2.4
p230
sg39
VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000aimmi value is +ve, -ve and zero\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of immi are toggled
p231
sg41
Visacov.rv32i_andi_cg.cp_rs1_value\u000aisacov.rv32i_andi_cg.cp_immi_value\u000aisacov.rv32i_andi_cg.cross_rs1_immi_value\u000aisacov.rv32i_andi_cg.cp_rs1_toggle\u000aisacov.rv32i_andi_cg.cp_immi_toggle
p232
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp233
sg15
(lp234
sg53
(lp235
sg13
(dp236
g56
I0
ssbtp237
a(V002
p238
g1
(g29
g3
Ntp239
Rp240
(dp241
g8
V002
p242
sg23
VVP_ISA_F011_S003_I002
p243
sg35
Vandi rd, rs1, imm[11:0]\u000ard = rs1 &  Sext(imm[11:0])\u000aNote: this is a bitwise, not logical operation
p244
sg37
VISA\u000aChapter 2.4
p245
sg39
VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled
p246
sg41
Visacov.rv32i_andi_cg.cp_rd_value\u000aisacov.rv32i_andi_cg.cp_rd_toggle
p247
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp248
sg15
(lp249
sg53
(lp250
sg13
(dp251
g56
I0
ssbtp252
asg88
(lp253
sg53
(lp254
sg13
(dp255
sbtp256
a(V004_SLTI
p257
g1
(g18
g3
Ntp258
Rp259
(dp260
g22
I3
sg8
g257
sg23
VVP_IP011_P004
p261
sg25
(dp262
sg12
I4
sg15
(lp263
(V000
p264
g1
(g29
g3
Ntp265
Rp266
(dp267
g8
V000
p268
sg23
VVP_ISA_F011_S004_I000
p269
sg35
Vslti rd, rs1, imm[11:0]\u000ard = (rs1 < Sext(imm[11:0]) ? 1 : 0\u000aBoth imm and rs1 treated as signed numbers
p270
sg37
VISA\u000aChapter 2.4
p271
sg39
VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used
p272
sg41
Visacov.rv32i_slti_cg.cp_rs1\u000aisacov.rv32i_slti_cg.cp_rd\u000aisacov.rv32i_slti_cg.cp_rd_rs1_hazard
p273
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp274
sg15
(lp275
sg53
(lp276
sg13
(dp277
g56
I0
ssbtp278
a(V001
p279
g1
(g29
g3
Ntp280
Rp281
(dp282
g8
V001
p283
sg23
VVP_ISA_F011_S004_I001
p284
sg35
Vslti rd, rs1, imm[11:0]\u000ard = (rs1 < Sext(imm[11:0]) ? 1 : 0\u000aBoth imm and rs1 treated as signed numbers
p285
sg37
VISA\u000aChapter 2.4
p286
sg39
VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000aimmi value is +ve, -ve and zero\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of immi are toggled
p287
sg41
Visacov.rv32i_slti_cg.cp_rs1_value\u000aisacov.rv32i_slti_cg.cp_immi_value\u000aisacov.rv32i_slti_cg.cross_rs1_immi_value\u000aisacov.rv32i_slti_cg.cp_rs1_toggle\u000aisacov.rv32i_slti_cg.cp_immi_toggle
p288
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp289
sg15
(lp290
sg53
(lp291
sg13
(dp292
g56
I0
ssbtp293
a(V002
p294
g1
(g29
g3
Ntp295
Rp296
(dp297
g8
V002
p298
sg23
VVP_ISA_F011_S004_I002
p299
sg35
Vslti rd, rs1, imm[11:0]\u000ard = (rs1 < Sext(imm[11:0]) ? 1 : 0\u000aBoth imm and rs1 treated as signed numbers
p300
sg37
VISA\u000aChapter 2.4
p301
sg39
VOutput result:\u000a\u000ard value is in [0,1]
p302
sg41
Visacov.rv32i_slti_cg.cp_rd_value
p303
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp304
sg15
(lp305
sg53
(lp306
sg13
(dp307
g56
I0
ssbtp308
asg88
(lp309
sg53
(lp310
sg13
(dp311
sbtp312
a(V005_SLTIU
p313
g1
(g18
g3
Ntp314
Rp315
(dp316
g22
I3
sg8
g313
sg23
VVP_IP011_P005
p317
sg25
(dp318
sg12
I5
sg15
(lp319
(V000
p320
g1
(g29
g3
Ntp321
Rp322
(dp323
g8
V000
p324
sg23
VVP_ISA_F011_S005_I000
p325
sg35
Vsltiu rd, rs1, imm[11:0]\u000ard = (rs1 < Sext(imm[11:0]) ? 1 : 0\u000aBoth imm and rs1 treated as unsigned numbers
p326
sg37
VISA\u000aChapter 2.4
p327
sg39
VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used
p328
sg41
Visacov.rv32i_sltiu_cg.cp_rs1\u000aisacov.rv32i_sltiu_cg.cp_rd\u000aisacov.rv32i_sltiu_cg.cp_rd_rs1_hazard
p329
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp330
sg15
(lp331
sg53
(lp332
sg13
(dp333
g56
I0
ssbtp334
a(V001
p335
g1
(g29
g3
Ntp336
Rp337
(dp338
g8
V001
p339
sg23
VVP_ISA_F011_S005_I001
p340
sg35
Vsltiu rd, rs1, imm[11:0]\u000ard = (rs1 < Sext(imm[11:0]) ? 1 : 0\u000aBoth imm and rs1 treated as unsigned numbers
p341
sg37
VISA\u000aChapter 2.4
p342
sg39
VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000aimmi value is +ve, -ve and zero\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of immi are toggled
p343
sg41
Visacov.rv32i_sltiu_cg.cp_rs1_value\u000aisacov.rv32i_sltiu_cg.cp_immi_value\u000aisacov.rv32i_sltiu_cg.cross_rs1_immi_value\u000aisacov.rv32i_sltiu_cg.cp_rs1_toggle\u000aisacov.rv32i_sltiu_cg.cp_immi_toggle
p344
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp345
sg15
(lp346
sg53
(lp347
sg13
(dp348
g56
I0
ssbtp349
a(V002
p350
g1
(g29
g3
Ntp351
Rp352
(dp353
g8
V002
p354
sg23
VVP_ISA_F011_S005_I002
p355
sg35
Vsltiu rd, rs1, imm[11:0]\u000ard = (rs1 < Sext(imm[11:0]) ? 1 : 0\u000aBoth imm and rs1 treated as unsigned numbers
p356
sg37
VISA\u000aChapter 2.4
p357
sg39
VOutput result:\u000a\u000ard value is in [0,1]
p358
sg41
Visacov.rv32i_sltiu_cg.cp_rd_value
p359
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp360
sg15
(lp361
sg53
(lp362
sg13
(dp363
g56
I0
ssbtp364
asg88
(lp365
sg53
(lp366
sg13
(dp367
sbtp368
a(V006_SLLI
p369
g1
(g18
g3
Ntp370
Rp371
(dp372
g22
I3
sg8
g369
sg23
VVP_IP011_P006
p373
sg25
(dp374
sg12
I6
sg15
(lp375
(V000
p376
g1
(g29
g3
Ntp377
Rp378
(dp379
g8
V000
p380
sg23
VVP_ISA_F011_S006_I000
p381
sg35
Vslli rd, rs, imm[4:0]\u000ard = rs << imm[4:0]\u000aZeros are shirfted into lower bits
p382
sg37
VISA\u000aChapter 2.4
p383
sg39
VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used
p384
sg41
Visacov.rv32i_slli_cg.cp_rs1\u000aisacov.rv32i_slli_cg.cp_rd\u000aisacov.rv32i_slli_cg.cp_rd_rs1_hazard
p385
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp386
sg15
(lp387
sg53
(lp388
sg13
(dp389
g56
I0
ssbtp390
a(V001
p391
g1
(g29
g3
Ntp392
Rp393
(dp394
g8
V001
p395
sg23
VVP_ISA_F011_S006_I001
p396
sg35
Vslli rd, rs, imm[4:0]\u000ard = rs << imm[4:0]\u000aZeros are shirfted into lower bits
p397
sg37
VISA\u000aChapter 2.4
p398
sg39
VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000aimmediate shamt value is [0,31]\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled
p399
sg41
Visacov.rv32i_slli_cg.cp_rs1_value\u000aisacov.rv32i_slli_cg.cp_immi_value\u000aisacov.rv32i_slli_cg.cross_rs1_immi_value\u000aisacov.rv32i_slli_cg.cp_rs1_toggle
p400
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp401
sg15
(lp402
sg53
(lp403
sg13
(dp404
g56
I0
ssbtp405
a(V002
p406
g1
(g29
g3
Ntp407
Rp408
(dp409
g8
V002
p410
sg23
VVP_ISA_F011_S006_I002
p411
sg35
Vslli rd, rs, imm[4:0]\u000ard = rs << imm[4:0]\u000aZeros are shirfted into lower bits
p412
sg37
VISA\u000aChapter 2.4
p413
sg39
VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled
p414
sg41
Visacov.rv32i_slli_cg.cp_rd_value\u000aisacov.rv32i_slli_cg.cp_rd_toggle
p415
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp416
sg15
(lp417
sg53
(lp418
sg13
(dp419
g56
I0
ssbtp420
asg88
(lp421
sg53
(lp422
sg13
(dp423
sbtp424
a(V007_SRLI
p425
g1
(g18
g3
Ntp426
Rp427
(dp428
g22
I4
sg8
g425
sg23
VVP_IP011_P007
p429
sg25
(dp430
sg12
I7
sg15
(lp431
(V000
p432
g1
(g29
g3
Ntp433
Rp434
(dp435
g8
V000
p436
sg23
VVP_ISA_F011_S007_I000
p437
sg35
Vsrli rd, rs, imm[4:0]\u000ard = rs >> imm[4:0]\u000aZeros are shirfted into upper bits
p438
sg37
VISA\u000aChapter 2.4
p439
sg39
VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used
p440
sg41
Visacov.rv32i_srli_cg.cp_rs1\u000aisacov.rv32i_srli_cg.cp_rd\u000aisacov.rv32i_srli_cg.cp_rd_rs1_hazard
p441
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp442
sg15
(lp443
sg53
(lp444
sg13
(dp445
g56
I0
ssbtp446
a(V001
p447
g1
(g29
g3
Ntp448
Rp449
(dp450
g8
g447
sg23
VVP_ISA_F011_S007_I001
p451
sg35
Vsrli rd, rs, imm[4:0]\u000ard = rs >> imm[4:0]\u000aZeros are shirfted into upper bits
p452
sg37
VISA\u000aChapter 2.4
p453
sg39
VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000aimmediate shamt value is [0,31]\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled
p454
sg41
Visacov.rv32i_srli_cg.cp_rs1_value\u000aisacov.rv32i_srli_cg.cp_immi_value\u000aisacov.rv32i_srli_cg.cross_rs1_immi_value\u000aisacov.rv32i_srli_cg.cp_rs1_toggle
p455
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp456
sg15
(lp457
sg53
(lp458
sg13
(dp459
g56
I0
ssbtp460
a(V002
p461
g1
(g29
g3
Ntp462
Rp463
(dp464
g8
g461
sg23
VVP_ISA_F011_S007_I002
p465
sg35
Vsrli rd, rs, imm[4:0]\u000ard = rs >> imm[4:0]\u000aZeros are shirfted into upper bits
p466
sg37
VISA\u000aChapter 2.4
p467
sg39
VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled
p468
sg41
Visacov.rv32i_srli_cg.cp_rd_value\u000aisacov.rv32i_srli_cg.cp_rd_toggle
p469
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp470
sg15
(lp471
sg53
(lp472
sg13
(dp473
g56
I0
ssbtp474
asg88
(lp475
sg53
(lp476
sg13
(dp477
sbtp478
a(V008_SRAI
p479
g1
(g18
g3
Ntp480
Rp481
(dp482
g22
I3
sg8
g479
sg23
VVP_IP011_P008
p483
sg25
(dp484
sg12
I8
sg15
(lp485
(V000
p486
g1
(g29
g3
Ntp487
Rp488
(dp489
g8
V000
p490
sg23
VVP_ISA_F011_S008_I000
p491
sg35
Vsrli rd, rs, imm[4:0]\u000ard = rs >> imm[4:0]\u000aThe original sign bit is copied into the vacated upper bits
p492
sg37
VISA\u000aChapter 2.4
p493
sg39
VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used
p494
sg41
Visacov.rv32i_srai_cg.cp_rs1\u000aisacov.rv32i_srai_cg.cp_rd\u000aisacov.rv32i_srai_cg.cp_rd_rs1_hazard
p495
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp496
sg15
(lp497
sg53
(lp498
sg13
(dp499
g56
I0
ssbtp500
a(V001
p501
g1
(g29
g3
Ntp502
Rp503
(dp504
g8
V001
p505
sg23
VVP_ISA_F011_S008_I001
p506
sg35
Vsrli rd, rs, imm[4:0]\u000ard = rs >> imm[4:0]\u000aThe original sign bit is copied into the vacated upper bits
p507
sg37
VISA\u000aChapter 2.4
p508
sg39
VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000aimmediate shamt value is [0,31]\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled
p509
sg41
Visacov.rv32i_srai_cg.cp_rs1_value\u000aisacov.rv32i_srai_cg.cp_immi_value\u000aisacov.rv32i_srai_cg.cross_rs1_immi_value\u000aisacov.rv32i_srai_cg.cp_rs1_toggle
p510
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp511
sg15
(lp512
sg53
(lp513
sg13
(dp514
g56
I0
ssbtp515
a(V002
p516
g1
(g29
g3
Ntp517
Rp518
(dp519
g8
V002
p520
sg23
VVP_ISA_F011_S008_I002
p521
sg35
Vsrli rd, rs, imm[4:0]\u000ard = rs >> imm[4:0]\u000aZeros are shirfted into upper bits
p522
sg37
VISA\u000aChapter 2.4
p523
sg39
VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled
p524
sg41
Visacov.rv32i_srai_cg.cp_rd_value\u000aisacov.rv32i_srai_cg.cp_rd_toggle
p525
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp526
sg15
(lp527
sg53
(lp528
sg13
(dp529
g56
I0
ssbtp530
asg88
(lp531
sg53
(lp532
sg13
(dp533
sbtp534
a(V009_LUI
p535
g1
(g18
g3
Ntp536
Rp537
(dp538
g22
I3
sg8
g535
sg23
VVP_IP011_P009
p539
sg25
(dp540
sg12
I9
sg15
(lp541
(V000
p542
g1
(g29
g3
Ntp543
Rp544
(dp545
g8
V000
p546
sg23
VVP_ISA_F011_S009_I000
p547
sg35
Vlui rd, imm[19:0]\u000ard = imm[19:0] << 12\u000ard[11:0] is zero-filled.
p548
sg37
VISA\u000aChapter 2.4
p549
sg39
VRegister operands:\u000a\u000aAll possible rd registers are used.
p550
sg41
Visacov.rv32i_lui_cg.cp_rd
p551
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp552
sg15
(lp553
sg53
(lp554
sg13
(dp555
g56
I0
ssbtp556
a(V001
p557
g1
(g29
g3
Ntp558
Rp559
(dp560
g8
V001
p561
sg23
VVP_ISA_F011_S009_I001
p562
sg35
Vlui rd, imm[19:0]\u000ard = imm[19:0] << 12\u000ard[11:0] is zero-filled.
p563
sg37
VISA\u000aChapter 2.4
p564
sg39
VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000aimmediate value is zero and non-zero\u000aAll bits of immu are toggled
p565
sg41
Visacov.rv32i_lui_cg.cp_immu_value\u000aisacov.rv32i_lui_cg.cp_immu_toggle
p566
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp567
sg15
(lp568
sg53
(lp569
sg13
(dp570
g56
I0
ssbtp571
a(V002
p572
g1
(g29
g3
Ntp573
Rp574
(dp575
g8
V002
p576
sg23
VVP_ISA_F011_S009_I002
p577
sg35
Vlui rd, imm[19:0]\u000ard = imm[19:0] << 12\u000ard[11:0] is zero-filled.
p578
sg37
VISA\u000aChapter 2.4
p579
sg39
VOutput result:\u000a\u000ard value is zero and non-zero\u000aAll bits of rd[31:12] are toggled (11:0 are deposited with 0)
p580
sg41
Visacov.rv32i_lui_cg.cp_rd_value\u000aisacov.rv32i_lui_cg.cp_rd_toggle
p581
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp582
sg15
(lp583
sg53
(lp584
sg13
(dp585
g56
I0
ssbtp586
asg88
(lp587
sg53
(lp588
sg13
(dp589
sbtp590
a(V010_AUIPC
p591
g1
(g18
g3
Ntp592
Rp593
(dp594
g22
I3
sg8
g591
sg23
VVP_IP011_P010
p595
sg25
(dp596
sg12
I10
sg15
(lp597
(V000
p598
g1
(g29
g3
Ntp599
Rp600
(dp601
g8
V000
p602
sg23
VVP_ISA_F011_S010_I000
p603
sg35
Vauipc rd, imm[19:0]\u000ard = pc + (imm[19:0] << 12)\u000apc is address of auipc instruction\u000a\u000aAssumption: arithmetic overflow is lost and ignored.
p604
sg37
VISA\u000aChapter 2.4
p605
sg39
VRegister operands:\u000a\u000aAll possible rd registers are used.
p606
sg41
Visacov.rv32i_auipc_cg.cp_rd
p607
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp608
sg15
(lp609
sg53
(lp610
sg13
(dp611
g56
I0
ssbtp612
a(V001
p613
g1
(g29
g3
Ntp614
Rp615
(dp616
g8
V001
p617
sg23
VVP_ISA_F011_S010_I001
p618
sg35
Vauipc rd, imm[19:0]\u000ard = pc + (imm[19:0] << 12)\u000apc is address of auipc instruction\u000a\u000aAssumption: arithmetic overflow is lost and ignored.
p619
sg37
VISA\u000aChapter 2.4
p620
sg39
VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000aimmediate value is zero and non-zero\u000aAll bits of immu are toggled
p621
sg41
Visacov.rv32i_auipc_cg.cp_immu_value\u000aisacov.rv32i_auipc_cg.cp_immu_toggle
p622
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp623
sg15
(lp624
sg53
(lp625
sg13
(dp626
g56
I0
ssbtp627
a(V002
p628
g1
(g29
g3
Ntp629
Rp630
(dp631
g8
V002
p632
sg23
VVP_ISA_F011_S010_I002
p633
sg35
Vauipc rd, imm[19:0]\u000ard = pc + (imm[19:0] << 12)\u000apc is address of auipc instruction\u000a\u000aAssumption: arithmetic overflow is lost and ignored.
p634
sg37
VISA\u000aChapter 2.4
p635
sg39
VOutput result:\u000a\u000ard value is zero and non-zero\u000aAll bits of rd[31:12] are toggled (11:0 are deposited with 0)
p636
sg41
Visacov.rv32i_auipc_cg.cp_rd_value\u000aisacov.rv32i_auipc_cg.cp_rd_toggle
p637
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp638
sg15
(lp639
sg53
(lp640
sg13
(dp641
g56
I0
ssbtp642
asg88
(lp643
sg53
(lp644
sg13
(dp645
sbtp646
asVrfu_list_0
p647
(lp648
sg88
(lp649
sVvptool_gitrev
p650
V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $
p651
sVio_fmt_gitrev
p652
V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $
p653
sVconfig_gitrev
p654
V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $
p655
sVymlcfg_gitrev
p656
V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $
p657
sbtp658
.